S1C17002 seiko epson corporation low power 16-bit single chip microcontroller low power mcu (operating voltage 1.8v power consumption sleep 0.5 ua, halt 3.3 ma) high code density and high processing pow er 16bitrisc c17cpu, optimize to c, serial ice 128kb rom, 8kb ram 10-bit adc infrared remote controller circuit ? descriptions the S1C17002 is a cost effective, high performance and comp act 16-bit risc application s pecific controller (asc). it is suitable for various products that require analog inputs and interfaces for connection, such as healthcare goods, sensor systems, alarms, home electric appliance (rice c ookers, microwave ovens and remote controllers). the S1C17002 consists of a s1c17 16-bit compact risc cpu core, a 128k-byte rom, an 8k-byte ram, a 10-bit adc with four analog input channels, a 16-bit multi-function timer, an infrared remote controlle r, serial interfaces (uart with irda 1.0 , spi and i2c), an rtc, 16-bit and 8-bit timers, a watchdog timer, and gpio ports. the S1C17002 provides a 16 bits 16 bits + 32 bits mac (mult iply and accumulate) and 16 bits 16 bits division functions to implement a dsp function. the S1C17002 has adopted the epson soc (syste m on chip) design technology using 0.18 m mixed analog low power cmos process. ? features cpu seiko epson original 16-bit risc processor s1c17 core internal 3-stage pipeline instruction set - 16-bit fixed length - 111 basic instructions (184 including variations) - compact and fast instruction se t optimized for development in c language registers - eight 24-bit general-purpose registers - three special registers (24-bit 2, 8-bit 1) memory space - up to 16m bytes accessible (24-bit address) internal memories mask rom - 128k bytes ram - 8k bytes operating clock main clock - 20 mhz (max.) - on-chip oscillator (crystal or ceramic) or external clock input sub clock - 32.768 khz (typ.) for the rtc, usable as the main clock - on-chip oscillator (crystal ) or external clock input interrupt controller four non-maskable interrupts - reset (#reset pin or watchdog timer) - address misaligned - debug - nmi (watchdog timer) 29 maskable interrupts - port inputs (eight systems) - 16-bit multi-function timer (one system) - a/d converter (two systems) - 16-bit timer of clock generator (one system) - 8-bit timers of clock generator (three systems) - uart (one system) - spi (one system)
S1C17002 2 seiko epson corporation - i2c master (one system) - i2c slave (two systems) - rtc (one system) - 8-bit programmable timers (four systems) - 8-bit osc1 timers (two systems) - extended spi (one system) - remote controller (one system) - the interrupt level (priority) of each maskable interrupt system is configurable (levels 0 to 7). prescaler generates the source clocks for the clock generator. 16-bit multi-function timer one channel of 16-bit timer/counter with pwm output function is available. can generate two compare-match interrupts. supports the igbt output control functi on using the a/d conver ter out-of-range signal. clock generator one channel of 16-bit timer and three channels of 8-bit timers are available. can be used as the clock source for the uart, spi, and i2c master. each timer can generate an underflow interrupt. 8-bit programmable timers four channels of 8-bit timers (presettable down counter) are available. can be used as an interval timer to trigger the adc. each timer can generate an underflow interrupt. 8-bit osc1 timers two channels of 8-bit timers (presettable down counte r) that are driven with the osc1 clock are available. each timer can generate an underflow interrupt. watchdog timer 30-bit watchdog timer to generate a reset or an nmi the watchdog timer overflow period (reset or nmi interrupt period) is programmable. the watchdog timer overflow signal can be output outside the ic. rtc contains time counters (second, minute, and hour) and ca lendar counters (day, day of the week, month, and year). periodic interrupts are possible. uart one channel of uart is available. supports irda 1.0 interface. two-byte receive data buffer and one-byte transmit buf fer are built in to suppor t full-duplex communication. transfer rate: 150 to 460800 bps, character length: seven or eight bits, parity mode: even, odd, or no parity, stop bit: one or two bits parity error, framing error, and overrun error detectable each channel can generate receive buffer full, tr ansmit buffer empty, and receive error interrupts. spi supports both master and slave modes. one-byte receive data buffer and one-byte transmit buffer are built in. data length: eight bits fixed (msb first) data transfer timing (clock phase and polarity variations) is selectable from among 4 types. can generate receive buffer full and transmit buffer empty interrupts. extended spi supports both master and slave modes. one-byte receive data buffer and one-byte transmit buffer are built in. data length: eight bits fixed (msb first) data transfer timing (clock phase and polarity variations) is selectable from among 4 types. can generate receive buffer full and transmit buffer empty interrupts. exclusive clock source is available. i 2 c master data format: 8 bits (msb first) addressing mode: 7-bit addressing (10-bit addressing is not supported.) incorporates a noise reject or (can be enabled by a register). can generate receive buffer full and transmit buffer empty interrupts. i 2 c slave data format: 8 bits (msb first) addressing mode: 7-bit addressing (10-bit addressing is not supported.) supports a clock stretch function incorporates a noise reject or (can be enabled by a register). can generate receive, trans mit, and bus status interrupts.
S1C17002 seiko epson corporation 3 infrared remote controller outputs a modulated carrier signal and inputs remote control pulses. embedded carrier signal gener ator and data length counter. can generates remc interrupts. general-purpose i/o ports maximum 30 i/o ports and four input ports are available. can generate input interrupts from t he six ports selected with software. * the gpio ports are shared with other peripheral function pins (uart, pwm et c.). therefore, the number of gpio ports depends on the peripher al functions used. a/d converter 10-bit a/d converter with up to four analog input ports can generates an end of conversion interrupt and an out of range interrupt. outputs an out of range signal to the igbt ci rcuit in the 16-bit multi-function timer module. operating voltage hvdd (for i/o): 1.65 to 3.60 v lvdd (for core): 1.65 to 1.95 v avdd (for adc): 2.70 to 3.60 v (1.65 to 3.60 v*) * the avdd voltage range can be changed to 1.65 to 3.60 v onl y when the adc is not used and the p0x pins are used as digital signal input pins, not analog input pins. howeve r, the high and low level input voltages of the digital signals must be avdd and gnd, respectively. operating temperatures -40 to 85 c current consumption during sleep: 1.8 a (typ.) 32 khz/1.8 v, rtc = on during halt: 1.3 ma (typ.) 20 mhz/1.8 v during execution: 3.8 ma (typ.) 20 mhz/1.8 v * by controlling the clocks through the clock-gear (cmu), power consum ption can be reduced. shipping form tqfp12-64pin (7 mm 7 mm 1.2 mm, 0.4 mm pin pitch) wcsp-48 (3.124 mm 3.124 mm 0.78 mm, 0.4 mm ball pitch) bare chip
S1C17002 4 seiko epson corporation ? block diagram semiconductor operations division seiko epson corporation ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042-587-5814 fax: 042-587-5117 notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko ep son. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. all brands or product names mentioned herein are trademarks and/ or registered trademarks of t heir respective companies. ?seiko epson corporation 2009, all rights reserved. http://www.epson.jp/device/semicon_e/ ? epson semiconductor website document code: 411826400 first issue oct, 2009 cpu core s1c17 ir am (8k bytes) mask rom (128k bytes) multiplier/divider (d sp ) i/o 1 (0x4000-) sram controller i/o 2 (0x4400-) prescaler clock generator uart spi i 2 c interrupt controller extended spi 16-bit multi-function ti mer 8-bit timer a/d converter remote controller clock management unit watchdog timer 8-b it osc1 timer rtc i/o port/ i/o mux i nte rrupt sys te m test # reset hv dd lv dd av dd vss spi_sdi1, spi_sdo1, spi_clk1, #spi_ssi1 excl0, tm0, #tm0, pwmprt 0 ain0-4, #adt rg remc_in, remc_out p00-03, p10-16, p20-27, p30-32, p35-37, p40-44, p50 -5 3 wdt _clk. #wdt_nmi osc1-2, osc3-4, cmu_clk i2cm_sda, i2cm_scl, i2cs_sda, i2cs_scl, #i2cs_rst spi_sdi0, spi_sdo0, spi_sck0, #spi_ssio sin0, sout0, #sclk0 dclk, dsio, dst2 cpu core s1c17 ir am (8k bytes) mask rom (128k bytes) multiplier/divider (d sp ) i/o 1 (0x4000-) sram controller i/o 2 (0x4400-) prescaler clock generator uart spi i 2 c interrupt controller extended spi 16-bit multi-function ti mer 8-bit timer a/d converter remote controller clock management unit watchdog timer 8-b it osc1 timer rtc i/o port/ i/o mux i nte rrupt sys te m test # reset hv dd lv dd av dd vss spi_sdi1, spi_sdo1, spi_clk1, #spi_ssi1 excl0, tm0, #tm0, pwmprt 0 ain0-4, #adt rg remc_in, remc_out p00-03, p10-16, p20-27, p30-32, p35-37, p40-44, p50 -5 3 wdt _clk. #wdt_nmi osc1-2, osc3-4, cmu_clk i2cm_sda, i2cm_scl, i2cs_sda, i2cs_scl, #i2cs_rst spi_sdi0, spi_sdo0, spi_sck0, #spi_ssio sin0, sout0, #sclk0 dclk, dsio, dst2
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